XR20M1280 Datasheet, PDF (7/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.0 FUNCTIONAL DESCRIPTIONS
1.1 CPU Interface
The XR20M1280 can operate with either an I²C-bus interface or an SPI interface. The CPU interface is
selected via the I2C/SPI# input pin.
1.1.1 I²C-bus Interface
The I²C-bus interface is compliant with the Standard-mode and Fast-mode I²C-bus specifications. The I²C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps. The first byte sent by an I²C-bus master contains a start bit (SDA transition from HIGH to LOW when
SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The XR20M1280 responds to each write with an
acknowledge (SDA driven LOW by XR20M1280 for one clock cycle when SCL is HIGH). If the TX FIFO is full,
the XR20M1280 will respond with a negative acknowledge (SDA driven HIGH by XR20M1280 for one clock
cycle when SCL is HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I²C-bus master
contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below. For
complete details, see the I²C-bus specifications.
FIGURE 3. I²C START AND STOP CONDITIONS
SDA
SCL
S
START condition
P
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE (XR20M1280)
S
SLAVE
ADDRESS
WA
REGISTER
ADDRESS
A
White block: host to UART
Grey block: UART to host
nDATA
AP
FIGURE 5. MASTER READS FROM SLAVE (XR20M1280)
S
SLAVE
ADDRESS
WA
White block: host to UART
Grey block: UART to host
REGISTER
ADDRESS
AS
SLAVE
ADDRESS
RA
nDATA
A
LAST DATA NA P
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