XR20M1280 Datasheet, PDF (10/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
The 128 byte TX FIFO can be loaded with data or 128 byte RX FIFO data can be unloaded in one SPI write or
read sequence.
FIGURE 8. SPI FIFO WRITE
SCL
SI R/W ‘0’ A2 A1 A0 ‘0’ ‘0’ X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
last bit
FIGURE 9. SPI FIFO READ
SCL
SI
R/W ‘0’ A2 A1 A0 ‘0’ ‘0’ X
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
last bit
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
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