XR20M1280 Datasheet, PDF (27/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
2.0 UART INTERNAL REGISTERS
The complete register set for the M1280 is shown in Table 9 and Table 10.
TABLE 9: UART INTERNAL REGISTERS
A2 A1 A0
0 00
0 00
0 01
0 10
0 00
0 01
0 10
0 11
1 00
1 01
1 01
1 10
1 10
1 11
1 11
1 11
0 00
0 00
0 01
0 10
1 00
1 01
1 10
1 11
1 00
1 01
1 10
1 11
REGISTER
READ/WRITE
16C550 COMPATIBLE REGISTERS
DREV - Device Revision
Read-only
DLL - Divisor LSB Register
DLM - Divisor MSB Register
DLD - Divisor Fractional Register
RHR - Receive Holding Register
THR - Transmit Holding Register
IER - Interrupt Enable Register
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read/Write
Read/Write
Read/Write
Read-only
Write-only
Read/Write
Read-only
Write-only
LCR - Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
SHR - Setup/Hysteresis Register
MSR - Modem Status Register
SFR - Special Function Register
Read/Write
Read/Write
Read-only
Write-only
Read-only
Write-only
SPR - Scratch Pad Register
Read/Write
EMSR - Enhanced Mode Select Register
Write-only
FC - RX/TX FIFO Level Counter Register
Read-only
ENHANCED REGISTERS
FC - RX/TX FIFO Level Counter Register
Read-only
TRIG - RX/TX FIFO Trigger Level Register
Write-only
FCTR - Feature Control Register
Read/Write
EFR - Enhanced Function Register
Read/Write
Xon-1 - Xon Character 1
Read/Write
Xon-2 - Xon Character 2
Read/Write
Xoff-1 - Xoff Character 1
Read/Write
Xoff-2 - Xoff Character 2
Read/Write
GPIOINT - GPIO Interrupt Enable Register
Read/Write
GPIO3T - GPIO Three-State Control Register Read/Write
GPIOINV - GPIO Polarity Control Register
Read/Write
GPIOSEL - GPIO Select Register
Read/Write
COMMENTS
LCR[7] = 1, LCR ≠ 0xBF,
DLL = 0x00, DLM = 0x00
LCR[7] = 1, LCR ≠ 0xBF
See DLD[7:6]
LCR[7] = 1, LCR ≠ 0xBF, EFR[4] = 1
LCR[7] = 0
LCR[7] = 0 if EFR[4] = 1
or
LCR ≠ 0xBF if EFR[4] = 0
LCR ≠ 0xBF
LCR ≠ 0xBF
EFR[4] = 1
LCR ≠ 0xBF, FCTR[6] = 0, SFR[0]=0
LCR ≠ 0xBF, FCTR[6] = 1, SFR[0]=0
LCR = 0xBF
LCR = 0xBF
SFR[0]=0
LCR = 0xBF
SFR[0]=1
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