XR20M1280 Datasheet, PDF (13/63 Pages) Exar Corporation – I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.3 Device Reset
The RESET# input resets the internal registers and the serial interface outputs to their default state (see
Table 21). An active low pulse of longer than 40 ns duration will be required to activate the reset function in the
device. Following a power-on reset or an external reset, the M1280 is software compatible with previous
generation of UARTs.
1.4 5-Volt Tolerant Inputs
The M1280 can accept and withstand 5V signals on the inputs without any damage. But note that if the supply
voltage for the M1280 is at the lower end of the supply voltage range (ie. 1.8V), its V_OH may not be high
enough to meet the requirements of the V_IH of a CPU or a serial transceiver that is operating at 5V. Caution:
XTAL1 is not 5 volt tolerant.
1.5 Internal Registers
The M1280 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.
These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),
a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control
registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible
scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the M1280 offers enhanced feature registers (EFR,
Xon1/Xoff1, Xon2/Xoff2, DLD, FCTR, EMSR, FC and TRIG, SFR, SHR, GPIOINT, GPIO3T, GPIOINV,
GPIOSEL) that provide automatic RTS and CTS hardware flow control, automatic Xon/Xoff software flow
control, 9-bit (Multidrop) mode, auto RS-485 half duplex control, different baud rate for TX and RX and
fractional baud rate generator. All the register functions are discussed in full detail later in “Section 2.0, UART
INTERNAL REGISTERS” on page 27.
1.6 IRQ# Ouput
The IRQ# interrupt output changes according to the operating mode and enhanced features setup. Table 4
and 5 summarize the operating behavior for the transmitter and receiver. Also see Figure 33 through 35.
IRQ# Pin
IRQ# Pin
TABLE 4: IRQ# PIN OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
NO
HIGH = One byte in THR HIGH = FIFO above trigger level
LOW = THR empty
LOW = FIFO below trigger level or FIFO empty
YES
HIGH = One byte in THR
LOW = THR empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
IRQ# Pin
TABLE 5: IRQ# PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
HIGH = One byte in THR
LOW = RHR empty
HIGH = FIFO above trigger level
LOW = FIFO above trigger level or RX Data Timeout
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