XR19L400 Datasheet, PDF (7/45 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

PRELIMINARY
XR19L400
REV. P1.0.0
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
2.2 5-Volt Tolerant Inputs
The CMOS/TTL level inputs of the L400 can accept up to 5V inputs when operating at 3.3V. Note that the
XTAL1 pin is not 5V tolerant when an external clock supply is used.
2.3 Device Hardware Reset
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see Table 14). An active pulse of longer than 40 ns duration will be required to activate the
reset function in the device.
2.4 Device Identification and Revision
The XR19L400 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x01 to
indicate functional compatibility with the XR16V2751 and reading the content of DLL will provide the revision of
the part; for example, a reading of 0x01 means revision A.
2.5 Channel Internal Registers
Each UART channel in the L400 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and an user accessible Scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the L400 offers enhanced feature registers just like the
XR16V2751, namely, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR and FC that provide automatic RTS
and CTS hardware flow control, Xon/Xoff software flow control, FIFO trigger level control and FIFO level
counters. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL
REGISTERS” on page 18.
2.6 DMA Mode
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR19L400. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
2.7 INT (IRQ#) Output
The interrupt output changes according to the operating mode and enhanced features setup. Table 1 and
Table 2 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola
modes. Also see Figures 18 through 21.
TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin 0 = one byte in THR
(I/M# = 1) 1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
IRQ# Pin 1 = one byte in THR
(I/M# = 0) 0 = THR empty
1 = FIFO above trigger level
0 = FIFO below trigger level or FIFO empty
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