XR19L400 Datasheet, PDF (6/45 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

XR19L400
PRELIMINARY
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. P1.0.0
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L400 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR19L400 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_ CS#
UART_ INT
R_ EN
ACP
PWRSAVE
UART_ RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW #
CS#
INT
R_EN
ACP
PWRSAVE
RESET
VCC3.3
VCC5.0
TX+
UART
Channel A
RX+
TX-
RX-
GND
VCC3.3
VCC5.0
RS-485 Interface
Intel Data Bus Interconnections
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
R/W#
UART_ CS #
UART_INT
R_ EN
ACP
PWRSAVE
UART_ RESET
VCC
VCC
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CS#
VCC3.3
VCC5.0
VCC3.3
VCC5.0
TX+
RX+
UART
Channel A ^TX-
RX-
RS-485 Interface
INT
R_EN
ACP
PWRSAVE
RESET
GND
Motorola Data Bus Interconnections
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