XR19L400 Datasheet, PDF (3/45 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

REV. P1.0.0
PIN DESCRIPTIONS
Pin Descriptions
PRELIMINARY
XR19L400
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
NAME
40-QFN
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
39
I _{Address bus lines [2:0]. These 3 address lines select one of the internal registers in the}
A1
40
UART during a data bus transaction.
A0
1
D7
9
I/O _{Data bus lines [7:0] (bidirectional).}
D6
8
D5
7
D4
6
D3
5
D2
4
D1
3
D0
2
IOR#
15
I _{When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read}
(NC)
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
IOW#
14
(R/W#)
I _{When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe}
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
CSA#
10
I _{When I/M# pin is HIGH, this input is chip select A (active low) to enable channel A in the}
(CS#)
device.
When I/M# pin is LOW, this input becomes the chip select (active low) for the Motorola bus
interface.
INTA
(IRQ#)
38
O _{When I/M# pin is HIGH, it selects Intel bus interface and this output become the active}
(OD) HIGH device interrupt output for channel A. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output for both channels. An external pull-up resistor is required
for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
SERIAL I/O INTERFACE (RS-485/RS-485 Voltage Levels)
TX+
TX-
RX+
RX-
32
O _{Differential UART Transmit Data.}
30
28
I _{Differential UART Receive Data.}
27
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
HALF/
34
FULL#
I _{When HALF/FULL# is HIGH, half-duplex mode is enabled.}
When HALF/FULL# is LOW, full-duplex mode is enabled.
XTAL1
12
I _{Crystal or external clock input.}
3