XR19L400 Datasheet, PDF (30/45 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

XR19L400
PRELIMINARY
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. P1.0.0
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11 Enhanced Mode Select Register (EMSR)
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Level Count (Write-Only)
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 10: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0] _{Scratchpad is}
0
X
X
Scratchpad
1
X
0
RX FIFO Level Counter Mode
1
0
1
TX FIFO Level Counter Mode
1
1
1
Alternate RX/TX FIFO Counter Mode
During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been
asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO
Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and
so on and so forth.
EMSR[3:2]: Reserved
EMSR[5:4]: Extended RTS Hysteresis
TABLE 11: AUTO RTS HYSTERESIS
EMSR
BIT-5
EMSR
BIT-4
FCTR
BIT-1
FCTR
BIT-0
RTS#
HYSTERESIS
(CHARACTERS)
0
0
0
0
0
0
0
0
1
±4
0
0
1
0
±6
0
0
1
1
±8
0
1
0
0
±8
0
1
0
1
±16
0
1
1
0
±24
0
1
1
1
±32
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