XR19L212 Datasheet, PDF (7/52 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L212
REV. 1.0.0
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L212 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 3.
FIGURE 3. XR19L212 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_ CSA#
UART_ CSB#
UART_ INTA
UART_ INTB
RXBSEL
R_EN
ACP
FAST
PWRSAVE
UART_ RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CSA#
CSB#
INTA
INTB
RXBSEL
R_EN
ACP
FAST
PWRSAVE
RESET
VCC
UART
Channel A
TXDA
RXDA
RTSA
CTSA
TXDB
RXDB
UART _RTSB
Channel B _CTSB
TXB
RXB
GND
Intel Data Bus Interconnections
VCC
RS -232 Interface
RS - 232 Interface
External IR or RS-422
Transceiver
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
R/W#
UART_ CS#
UART_ IRQ#
RXBSEL
R_EN
ACP
FAST
PWRSAVE
UART_ RESET
VCC
VCC
(no connect)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSB#
IOR#
IOW #
CSA#
INTA
INTB
RXBSEL
R_EN
ACP
FAST
PWRSAVE
RESET
VCC
TXDA
RXDA
UART
Channel A ^RTSA
CTSA
TXDB
RXDB
UART
RTSB
Channel B
CTSB
TXB
RXB
GND
Motorola Data Bus Interconnections
VCC
RS - 232 Interface
RS - 232 Interface
External IR or RS- 422
transceiver
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