XR19L212 Datasheet, PDF (15/52 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L212
REV. 1.0.0
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
2.12.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
2.12.2 Selectable Input to RX of Channel B
There is an input (RXBSEL) that selects whether the signal going to the RXB input of the UART will be the
signal from the RS-232 transceiver or not. If RXBSEL is LOW, then the signal to the RXB input is the RXDB
signal from the RS-232 transceiver. When RXDB is used, the RXB input should be left floating. The signal
received at the UART can be probed at the RXB pin. If RXBSEL is HIGH, then the RXDB pin is tri-stated and
RXB can be used with an external Infrared transceiver or RS-422 transceiver. If RXB is selected but is unused,
RXB should be connected to VCC. See Figure 6 for a detailed drawing.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X Clock
(EMSR bit-7)
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
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