XR19L212 Datasheet, PDF (14/52 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L212
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
REV. 1.0.0
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X or 8X
Clock
(EMSR Bit-7)
Transmit Shift Register (TSR)
M
L
S
S
B
B
TXNOFIFO1
2.11.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
T ra n sm it
Data Byte
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
Auto Software Flow Control
T ra n s m it
FIFO
THR Interrupt (ISR bit-1) falls
below the programm ed Trigger
Level and then when becomes
em pty. FIFO is Enabled by FCR
bit-0=1
16X or 8X Clock
(EMSR bit-7)
Transm it Data Shift Register
(TSR)
TXFIFO 1
2.12 RECEIVER
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X clock (EMSR bit-7) for timing. It verifies
and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or
false start bit, an internal receiver counter starts counting at the 16X/8X clock rate. After 8 clocks (or 4 if 8X) the
start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic
0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character.
The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing.
If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte
from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status
of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character
or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
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