XR17D152IM-F Datasheet, PDF (67/68 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART

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UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
XR17D152
REV. 1.2.0
5.2.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 27
5.2.4 AUTO RS485 OPERATION ........................................................................................................................................ 27
FIGURE 12. TRANSMITTER OPERATION IN NON-FIFO MODE ............................................................................................................ 27
5.3 RECEIVER ...................................................................................................................................................... 28
5.3.1 RECEIVE HOLDING REGISTER (RHR) ..................................................................................................................... 28
FIGURE 13. TRANSMIITTER OPERATION IN FIFO AND FLOW CONTROL MODE................................................................................... 28
5.3.2 RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................... 29
5.3.3 RECEIVER OPERATION WITH FIFO......................................................................................................................... 29
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................. 29
FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ......................................................................................... 29
5.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .............................. 30
TABLE 10: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION .......................................................................................... 30
FIGURE 16. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION...................................................................................... 31
5.5 INFRARED MODE .......................................................................................................................................... 32
FIGURE 17. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 32
5.6 INTERNAL LOOPBACK ................................................................................................................................. 33
5.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ...................................... 33
FIGURE 18. INTERNAL LOOP BACK FUNCTION IN EACH UART CHANNEL .......................................................................................... 33
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS ................................................................................................... 34
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 35
5.8 REGISTERS .................................................................................................................................................... 36
5.8.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 36
5.8.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 36
5.8.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE................................................................ 36
5.8.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE.......................................................................................... 36
IER versus Receive FIFO Interrupt Mode Operation................................................................................................. 36
IER versus Receive/Transmit FIFO Polled Mode Operation ..................................................................................... 36
5.8.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY............................................................................................ 37
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 38
5.8.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY.................................................................................................. 39
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 40
5.8.7 LINE CONTROL REGISTER (LCR) - READ/WRITE.................................................................................................. 41
5.8.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE ........................................................................................... 42
TABLE 15: PARITY SELECTION ........................................................................................................................................................ 42
5.8.9 LINE STATUS REGISTER (LSR) - READ/ONLY ....................................................................................................... 43
5.8.10 MODEM STATUS REGISTER (MSR) - READ-ONLY .............................................................................................. 44
5.8.11 MODEM STATUS REGISTER (MSR) - WRITE-ONLY ............................................................................................. 45
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 45
5.8.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE................................................................................................. 46
5.8.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE.................................................................................... 46
5.8.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE..................................................................................... 47
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 47
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 48
5.8.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ-ONLY ......................................................................... 49
5.8.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE-ONLY ........................................................................ 49
5.8.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ-ONLY............................................................................ 49
5.8.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE-ONLY............................................................................ 49
TABLE 19: UART RESET CONDITIONS ...................................................................................................................................... 50
6.0 PROGRAMMING EXAMPLES ............................................................................................................. 51
6.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS .................. 51
ABSOLUTE MAXIMUM RATINGS .................................................................................. 52
ELECTRICAL CHARACTERISTICS................................................................................ 52
DC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5-5.5V)
52
AC ELECTRICAL CHARACTERISTICS FOR 5V PCI BUS INTERFACE (VIO = 4.75-5.25V, VCC = 4.5-5.5V)
53
ELECTRICAL CHARACTERISTICS................................................................................ 54
DC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V)54
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V)55
FIGURE 19. TIMING FOR EXTERNAL CLOCK INPUT AT XTAL1 PIN.................................................................................................... 56
FIGURE 20. PCI BUS CONFIGURATION SPACE REGISTERS READ AND WRITE OPERATION................................................................. 57
FIGURE 21. DEVICE CONFIGURATION AND UART REGISTERS READ OPERATION FOR A BYTE OR DWORD ...................................... 58
FIGURE 22. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND TRANSMIT DATA BURST WRITE OPERATION ..................... 59
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