XR17D152IM-F Datasheet, PDF (30/68 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART

XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
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REV. 1.2.0
5.4 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver
FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request the remote unit to suspend/
restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart the local transmitter.
The auto RTS/CTS or DTR/DSR flow control features are individually selected to fit specific application
requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS or DTR/DSR control
signals.
TABLE 10: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION
MCR BIT-2
EFR BIT-7
EFR BIT-6
HARDWARE FLOW CONTROL SELECTION
0
1
X
Auto CTS Flow Control Enabled
0
X
1
Auto RTS Flow Control Enabled
1
1
X
Auto DSR Flow Control Enabled
1
X
1
Auto DTR Flow Control Enabled
X
0
0
No Hardware Flow Control
Auto RTS flow control must be started by asserting the RTS# output pin LOW (MCR bit-1 = 1). Similarly, Auto
DTR flow control must be started by asserting the DTR# output pin LOW (MCR bit-0 = 1). Figure 16 shows in
detail how automatic hardware flow control works.
Two interrupts associated with auto RTS/CTS and DTR/DSR flow control have been added to give indication
when RTS#/DTR# pin or CTS#/DSR# pin are de-asserted during operation. These interrupts are enabled by:
• Setting EFR bit-4 =1 to enable the shaded register bits
• Setting IER bit-7 will enable the CTS#/DSR# interrupt when these pins are de-asserted. The selection of
CTS# or DSR# is selected via MCR bit-2. See Table 10 above for complete details.
• Setting IER bit-6 will enable the RTS#/DTR# interrupt when these pins are de-asserted. The selection of
RTS# or DTR# is selected via MCR bit-2. See Table 10 above for complete details.
Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1.
If CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit-5 will be set to logic 1, (if
enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns LOW, indicating more data may
be sent.
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