XR17D152IM-F Datasheet, PDF (66/68 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART

XR17D152
REV. 1.2.0
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UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PIN OUT OF THE XR17D152 ........................................................................................................................................... 2
ORDERING INFORMATION.................................................................................................................................2
PIN DESCRIPTIONS.........................................................................................................................................3
PCI LOCAL BUS INTERFACE.....................................................................................................................3
MODEM OR SERIAL I/O INTERFACE ........................................................................................................3
ANCILLARY SIGNALS.................................................................................................................................4
FUNCTIONAL DESCRIPTION ...........................................................................................6
PCI Local Bus Interface ............................................................................................................................................... 6
PCI Local Bus Configuration Space Registers ............................................................................................................ 6
EEPROM Interface ...................................................................................................................................................... 6
1.0 APPLICATION EXAMPLES ...................................................................................................................7
FIGURE 3. TYPICAL APPLICATION FOR A UNIVERSAL ADD-IN CARD .................................................................................................... 7
FIGURE 4. TYPICAL APPLICATIONS IN AN EMBEDDED SYSTEM............................................................................................................ 8
2.0 XR17D152 REGISTERS .........................................................................................................................9
FIGURE 5. THE XR17D152 REGISTER SETS..................................................................................................................................... 9
2.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS .......................................................................... 10
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ....................................................................................................... 10
2.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................. 11
TABLE 2: XR17D152 DEVICE CONFIGURATION REGISTERS............................................................................................................. 12
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ................................................................................... 12
TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT............................................................................... 13
2.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 14
FIGURE 6. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 .................................................................................. 15
TABLE 5: UART CHANNEL [1:0] INTERRUPT SOURCE ENCODING ..................................................................................................... 15
TABLE 6: UART CHANNEL [1:0] INTERRUPT CLEARING: .................................................................................................................. 15
2.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
00-00).............................................................................................................................................................................. 16
FIGURE 7. TIMER/COUNTER CIRCUIT............................................................................................................................................... 16
TABLE 7: TIMER CONTROL REGISTERS ...................................................................................................................................... 16
2.2.3 8XMODE [7:0] (DEFAULT 0X00)................................................................................................................................ 17
2.2.4 REGA [15:8] RESERVED ........................................................................................................................................... 17
2.2.5 RESET [23:16] - (DEFAULT 0X00)............................................................................................................................. 17
2.2.6 SLEEP [31:24] - (DEFAULT 0X00)............................................................................................................................. 18
2.2.7 DEVICE IDENTIFICATION AND REVISION ............................................................................................................... 19
2.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS .............................................................................................................. 19
2.2.10 MPIO REGISTER ...................................................................................................................................................... 19
2.2.8 REGB REGISTER ....................................................................................................................................................... 19
FIGURE 8. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT ........................................................................................................... 20
3.0 CRYSTAL OSCILLATOR / BUFFER ...................................................................................................22
FIGURE 9. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 22
FIGURE 10. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE ........................................................................................ 22
4.0 TRANSMIT AND RECEIVE DATA .......................................................................................................23
4.1 DATA LOADING AND UNLOADING VIA 32-BIT PCI BURST TRANSFERS ............................................... 23
4.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100 (CHANNEL 0) AND 0X300 (CHANNEL 1)........ 23
4.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180 (CHANNEL 0) AND 0X380 (CHANNEL 1) ........ 24
4.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100 (CHANNEL 0) AND 0X300 (CHANNEL 1) .............................. 24
4.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN
8-BIT FORMAT ............................................................................................................................................... 25
5.0 UART ....................................................................................................................................................25
5.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 25
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE ............................................................ 25
FIGURE 11. BAUD RATE GENERATOR ............................................................................................................................................. 26
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING .......................................... 26
5.2 TRANSMITTER ............................................................................................................................................... 27
5.2.1 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY......................................................................................... 27
5.2.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 27
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