XR17D152IM-F Datasheet, PDF (3/68 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART

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REV. 1.2.0
XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
PIN DESCRIPTIONS
NAME
PIN #
PCI LOCAL BUS INTERFACE
RST#
86
CLK
87
TYPE
DESCRIPTION
I PCI Bus reset input (active low). It resets the PCI local bus configuration
space registers, device configuration registers and UART channel registers
to the default condition, see Table 19 on page 50.
I PCI Bus clock input of up to 33.34MHz.
AD31-AD24,
AD23-AD16,
AD15-AD8,
AD7-AD0
90-97,
2-9,
24-31,
35-42
I/O Address data lines [31:0] (bidirectional).
FRAME#
13
I Bus transaction cycle frame (active low). It indicates the beginning and dura-
tion of an access.
C/BE3#-
C/BE0#
IRDY#
TRDY#
98, 12,
21, 34
14
15
I Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus
Command during the address phase and Byte Enables during the data
phase.
I Initiator Ready (active low). During a write, it indicates that valid data is
present on data bus. During a read, it indicates the master is ready to accept
data.
O Target Ready (active low).
STOP#
17
O Target request to stop current transaction (active low).
IDSEL
99
I Initialization device select (active high).
DEVSEL#
INTA#
16
O Device select to the XR17D152 (active low).
85
OD Device interrupt from XR17D152 (open drain, active low).
PAR
20
I/O Parity is even across AD[31:0] and C/BE[3:0]#. (bidirectional, active high).
PERR#
18
O
SERR#
19
OD
MODEM OR SERIAL I/O INTERFACE
TX0
73
O
RX0
66
I
RTS0#
71
O
Data Parity error indicator, except for Special Cycle transactions (active low).
Optional in bus target application.
System error indicator, Address parity or Data parity during Special Cycle
transactions (open drain, active low). Optional in bus target application.
UART channel 0 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles HIGH while infrared RXD input idles LOW. In the infrared mode, the
polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit
is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a
logic 1, a HIGH on the RXD input is considered a space.
UART channel 0 Request to Send or general purpose output (active low). If
this output is not used, leave it unconnected.
CTS0#
67
I UART channel 0 Clear to Send or general purpose input (active low). This
input should be connected to VCC when not used.
DTR0#
72
O UART channel 0 Data Terminal Ready or general purpose output (active
low). If this output is not used, leave it unconnected.
3