XRT84L38 Datasheet, PDF (6/451 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER

XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.0
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3.2 T1 EXTENDED SUPERFRAME FORMAT ................................................................................................. 193
Figure 22. T1 Extended Superframe Format ................................................................................ 193
TABLE 34: EXTENDED SUPERFRAME FORMAT .................................................................................... 194
3.3 SLC 96 FORMAT (SLC) ...................................................................................................................... 195
TABLE 35: SLC®96 FS BIT CONTENTS ............................................................................................. 195
4.0 The DS1 Transmit Section ................................................................................................................... 196
4.1 THE DS1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ............................................................ 196
4.1.1 Description of the Transmit Payload Data Input Interface Block ............................................. 196
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 196
4.1.2 Brief Discussion of the Transmit Payload Data Input Interface Block Operating at 1.544Mbit/s
mode ................................................................................................................................................ 197
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 197
TABLE 36: SIGNALS FOR DIFFERENT TRANSMIT TIMING SOURCES ........................................................ 198
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 198
TABLE 37: THE TXTSB[3:0] BITS WHEN THE TRANSMIT FRACTIONAL T1 INPUT BIT IS SET TO DIFFERENT VAL-
UES ...................................................................................................................................... 199
Figure 23. Interfacing XRT84L38 to local Terminal Equipment with TxSerClk_n as Transmit Tim-
ing Source .......................................................................................................................... 200
Figure 24. Waveforms of the signals that connect the Transmit Payload Data Input Interface
block to the local Terminal Equipment with the Transmit Serial clock being the Timing
Source of the Transmit Section ....................................................................................... 201
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................ 202
Figure 25. Interfacing XRT84L38 to the local Terminal Equipment with the OSCCLK Driven Divid-
ed Clock as Transmit Timing Source .............................................................................. 203
Figure 26. Waveforms of the signals connecting the Transmit Payload Data Input Interface block
to the local Terminal Equipment with the OSCCLK Driven Divided clock as the timing
source of the Transmit Section ....................................................................................... 204
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................. 205
Figure 27. Interfacing XRT84L38 to local Terminal Equipment with Recovered Receive Line
Clock as Transmit Timing Source ................................................................................... 206
4.1.3 Brief Discussion of the Transmit High-Speed Back-Plane Interface ....................................... 207
Figure 28. Waveforms of the signals connecting the Transmit Payload Data Input Interface block
to the local Terminal Equipment with the Recovered Receive Line Clock being the timing
source of the Transmit Section ....................................................................................... 207
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 207
TABLE 38: TRANSMIT MULTIPLEX ENABLE BIT AND TRANSMIT INTERFACE MODE SELECT [1:0] BITS WITH THE
RESULTING TRANSMIT BACK-PLANE INTERFACE DATA RATES ................................................. 208
TRANSMIT MULTIPLEX ENABLE BIT = 0 ...................................................................................................... 208
TRANSMIT MULTIPLEX ENABLE BIT = 1 ...................................................................................................... 209
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 209
TABLE 39: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 210
Figure 29. Interfacing XRT84L38 to the local Terminal Equipment using MVIP 2.048Mbit/s Data
Bus ..................................................................................................................................... 211
Figure 30. Timing Diagram of the Input Signals to the Framer when running at MVIP 2.048Mbit/s
Mode ................................................................................................................................... 211
TABLE 40: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 212
Figure 31. Interfacing XRT84L38 to the local Terminal Equipment using 4.096Mbit/s Data Bus ..
213
Figure 32. Timing Diagram of the Input Signals to the Framer when running at 4.096Mbit/s Mode
213
TABLE 41: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ..................................................... 214
Figure 33. Interfacing XRT84L38 to the Local Terminal Equipment using 8.192Mbit/s Data Bus .
215
Figure 34. Timing Diagram of the Input Signals to the Framer when running at 8.192Mbit/s Mode
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