XRT84L38 Datasheet, PDF (1/451 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER

áç
XRT84L38
FEBRUARY 2004
OCTAL T1/E1/J1 FRAMER
REV. 1.0.0
GENERAL DESCRIPTION
The XRT84L38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framing controller. The
XRT84L38 contains an integrated DS1/E1/J1 framer
which provides DS1/E1/J1 framing and error accumu-
lation in accordance with ANSI/ITU_T specifications.
Each framer has its own framing synchronizer and
transmit-receive slip buffers, and can be independent-
ly enabled or disabled as required and can be config-
ured to frame to the common DS1/E1/J1 signal for-
mats
Each Framer block contains its own Transmit and Re-
ceive T1/E1/J1 Framing function including 3 HDLC
controllers to support V5.2. Each Transmit HDLC
controller encapsulates contents of the Transmit
HDLC buffers into LAPD Message frames. Each Re-
ceive HDLC controller extracts payload content of Re-
ceive LAPD Message frames from the incoming T1/
E1/J1 data stream and writes it into the Receive
HDLC buffer. Each framer also contains a Transmit
and Overhead Data Input port, which permits Data
Link Terminal Equipment direct access to the out-
bound T1/E1/J1 frames Likewise, a Receive Over-
head output data port permits Data Link Terminal
Equipment direct access to the Data Link bits of the
inbound T1/E1/J1 frames.
The XRT84L38 fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan, Pseu-
do Random bit sequence (PRBS) test pattern gener-
ation, Performance Monitor, Bit Error Rate (BER)
meter, forced error insertion, and LAPD unchannel-
ized data payload processing according to ITU-T
standard Q.921.
Applications and Features (next page)
FIGURE 1. XRT84L38 8-CHANNEL DS1 (T1/E1/J1) FRAMER
Local PCM
Highway
XRT84L38
1 of 8-channels
8
Tx Serial
Clock
Tx Serial
Data In
8
Rx Serial
Clock
Rx Serial
Data Out
PRBS
Generator &
Analyser
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
2-Frame
Slip Buffer
Elastic Store
Tx Framer
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Performance
Monitor
HDLC (LAPD)
Controller &
96-byte Buffer
Tx Encoder
LIU
Interface
LLB LB
Rx Encoder
LIU
Interface
LIU &
Loopback
Control
TxPOS 8
TxNEG 8
TxLineCLK 8
8 DS1/E1
Channels
1.544/2.048 MHz
XRT83L38
TPOS
TNEG
Tx1
TCLK1
Twisted
Pair
RxPOS 8
RxNEG 8
RxLineCLK 8
Rx1
RPOS
RNEG
RCLK1
µP
Interface
Tx8
Twisted
Pair
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Signaling &
Alarms
System (Terminal) Side
JTAG
DMA
Interface
Microprocessor
Interface
Interrupt
D[7:0]
Memory
A[6:0]
3
Channel
Select
4 ^WR
ALE_AS
RD
RDY_DTACK
Intel/Motorola µP
Configuration, Control &
Status Monitor
Rx8
8-CH T1/E1/LIU
Host Mode
Line Side
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • [phone] • FAX [phone] • www.exar.com