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| XRT84L38 Datasheet, PDF (315/451 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER | |||
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XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.0
The following table illustrates how payload bits and signaling bits are multiplexed together into the
16.384Mbit/s data stream.
SECOND OCTET OF 16.384MBIT/S DATA STREAM
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
50
A0
60
B0
70
C0
80
D0
FOURTH OCTET OF 16.384MBIT/S DATA STREAM
BIT 0
BIT 1
BIT 2
BIT 3
51
A1
61
B1
BIT 4
71
BIT 5
C1
BIT 6
81
BIT 7
D1
SIXTH OCTET OF 16.384MBIT/S DATA STREAM
BIT 0
BIT 1
BIT 2
BIT 3
52
A2
62
B2
BIT 4
72
BIT 5
C2
BIT 6
82
BIT 7
D2
EIGHTH OCTET OF 16.384MBIT/S DATA STREAM
BIT 0
BIT 1
BIT 2
BIT 3
53
A3
63
B3
BIT 4
73
BIT 5
C3
BIT 6
83
BIT 7
D3
XY: The Xth payload bit of Channel Y
AY: The signaling bit A of Channel Y
3. After the first octets of all four channels are sent, the Receive High-speed Back-plane Interface will start
sending the second octets following the same rules of Step 1 and 2.
The Receive Single-frame Synchronization signal should pulse HIGH for four clock cycles (the last two bit posi-
tions of the previous multiplexed frame and the first two bits of the next multiplexed frame) indicating frame
boundary of the multiplexed data stream. The Receive Single-frame Synchronization signal of Channel 0 puls-
es HIGH to identify the start of multiplexed data stream of Channel 0-3. The Receive Single-frame Synchroni-
zation signal of Channel 0 pulses HIGH to identify the start of multiplexed data stream of Channel 0-3. By sam-
pling the HIGH pulse of the Receive Single-frame Synchronization signal, the Receive High-speed Back-plane
Interface of the framer can identify the beginning of a multiplexed frame and can start sending payload data of
that frame.
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