XRT84L38 Datasheet, PDF (447/451 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER

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XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.0
will be used to carry data link information or CAS signals. The table below shows configuration of the Receive
Signaling and Data Link Control [2:0] bits of the Receive Signaling and Data Link Select Register (RSDLSR).
RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H,
0X0CH)
BIT
NUMBER
2-0
BIT NAME
BIT TYPE
BIT DESCRIPTION
Receive Signaling
and Data Link
Select
R/W 000 - Timeslot 16 octet is extracted directly to the Receive Serial Output
Interface through the RxSer_n pin.
001 - Timeslot 16 octet is extracted directly to the Receive Overhead Out-
put Interface through the RxOH_n pin or the Receive Signaling Control
Register of Timeslot 16.
010 - Timeslot 16 octet is extracted directly to the Receive Serial Output
Interface through the RxSer_n pin.
011 - Timeslot 16 octet is extracted directly to the Receive Overhead Out-
put Interface through the RxOH_n pin or the Receive Signaling Control
Register of Timeslot 16.
1xx - Timeslot 16 octet is extracted to the data link interface.
If the Receive Signaling and Data Link Select [2:0] bits of the Receive Signaling and Data Link Select Register
are set to 1xx, the data link interface becomes destination of the Timeslot 16 octet.
14.2.4 How to configure XRT84L38 to receive data link information through D or E Channels
The XRT84L38 can configure any one or ones of the thirty-two E1 channels to be D or E channels except for
Channel number 0. D channel is used primarily for data link applications. E channel is used primarily for signal-
ing for circuit switching with multiple access configurations.
The Receive Conditioning Select [3:0] bits of the Receive Channel Control Register (RCCR) of each channel
determine whether that particular channel is configured as D or E channel. These bits also determine what
type of data or signaling conditioning is applied to each channel.
RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH)
BIT
NUMBER
BIT NAME
BIT TYPE
BIT DESCRIPTION
3-0 Receive Condition- R/W 1111 - This channel is configured as D or E timeslot.
ing Select
If the Receive Conditioning Select [3:0] bits of the Receive Channel Control Register of a particular timeslot are
set to 1111, that timeslot is configured as a D or E timeslot.
NOTE: Timeslot 0 can never be configured as D or E timeslot.
14.2.5 Receive BOS (Bit Oriented Signaling) Processor
The Receive BOS Processor handles receiving and processing of BOS messages through the E1 data link
channel. It generates Receive End of Transfer (RxEOT) interrupt each time a BOS message is received and
stores the BOS message into the receive message buffer. Please see Section ? for how to configure the BOS
Processor Block to receive BOS message.
14.2.6 Receive LAPD Controller
The receive LAPD controller implements the Message-Oriented protocol based on ITU Recommendation
Q.921 Link Access Procedures on the D-channel (LAPD) type of protocol. It provides the following functions:
• Zero deletion
• Pattern recognition for IDLE flag detection
• Pattern recognition for ABORT sequence detection
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