XR21B1411IL-0A-EB Datasheet, PDF (6/30 Pages) Exar Corporation – ENHANCED 1-CH FULL-SPEED USB UART

XR21B1411
ENHANCED 1-CH FULL-SPEED USB UART
REV. 1.2.0
1.3.1 Transmitter
The transmitter consists of a 128-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet
has been received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO.
Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous
data byte. The TSR shifts the data out onto the TX output pin at the selected baud rate. The transmitter sends
the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds
the stop-bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without
parity.
If 7 or 8 bit data with parity is selected, the TX FIFO contains 8 bits data and the parity bit is automatically
generated and transmitted. If 9 bit data is selected, parity cannot be generated. The 9th bit will always be a ’0’
unless the wide mode is enabled.
1.3.1.1
Wide mode Transmit
When 9 bit data and the wide mode are both selected, 2 bytes from the USB host are used to form 9 bit data
which is serialized and transmitted on the UART TX pin. The first byte received into the TX FIFO forms the first
8 bits of data and the least significant bit of the second byte forms the 9th data bit. The remaining 7 bits of the
second byte are discarded. The wide mode can be enabled via the WIDE_MODE register at address 0xD02.
1.3.2 Receiver
The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the
RSR via the RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host in
response to a bulk-in request. Depending on the mode, error / status information for that data character may
or may not be stored in the RX FIFO with the data.
1.3.2.1
Normal receive operation with 7 or 8-bit data
Data that is received is stored in the RX FIFO. Any parity, framing or overrun error or break status information
related to the data is discarded. Receive data format is shown in Figure 3.
1.3.2.2
Normal receive operation with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun
error or break status information related to the data is discarded.
FIGURE 3. NORMAL OPERATION RECEIVE DATA FORMAT
7, 8, or 9 bit data
1^ST byte 7 6 5 4 3 2 1 0 _{7=‘0’ in7bit mode}
1.3.2.3
Wide mode operation with 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received
data. The second byte consists of the error bits and break status. Wide mode receive data format is shown in
Figure 4.
1.3.2.4
Wide mode operation with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of
the received data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received /
checked. The remainder of the 2nd byte consists of the framing and overrun error bits and break status.
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