XR21B1411IL-0A-EB Datasheet, PDF (24/30 Pages) Exar Corporation – ENHANCED 1-CH FULL-SPEED USB UART

XR21B1411
ENHANCED 1-CH FULL-SPEED USB UART
3.2.1 OTP Memory Descriptions
REV. 1.2.0
Some OTP memory locations are pre-programmed at the factory before shipments to customers.
Programming any memory location other than those specified below may result in permanent damage to the
device.
3.2.1.1
OTP Config0 (Read / Write OTP)
OTP_CONFIG0[0]: Reserved
 Factory programmed - overwriting this bit may cause functional damage to the B1411 device
OTP_CONFIG0[1]: Lowpower_Pol
 Sets the polarity of the LOWPOWER output pin
•Logic 0 = LOWPOWER output pin will be active low
•Logic 1 = LOWPOWER output pin will be active high
OTP_CONFIG0[7:2]: Reserved
 Factory programmed - overwriting these bits may cause functional damage to the B1411 device
3.2.1.2
OTP Config1 (Read / Write OTP)
OTP_CONFIG1[7:0]: Reserved
 Factory programmed - overwriting these bits may cause functional damage to the B1411 device
3.2.1.3
OTP Config2 (Read / Write OTP)
OTP_CONFIG2[7:0]: Reserved
 Factory programmed - overwriting these bits may cause functional damage to the B1411 device
3.2.1.4
OTP Config3 (Read / Write OTP)
OTP_CONFIG3[2:0]: Core_Clock_Select
The B1411 core can run at a fraction of the 48 MHz bus clock to minimize power consumption in the core.
Refer to Table 12 for core clock divider settings. Note that the selected core clock rate must be a minimum of
4x the maximum baud rate setting desired in a customer application. For example, if a core clock of 6 MHz is
selected, the maximum baud rate of the B1411 is 1.5 Mbps.
TABLE 12: CORE CLOCK DIVIDER
VALUE
NAME
DESCRIPTION
3'b000
DIV_BY_1 Core Clock = CLOCK / 1 (48 MHz)
3'b001
DIV_BY_2 Core Clock = CLOCK / 2 (24 MHz)
3'b010
DIV_BY_4 Core Clock = CLOCK / 4 (12 MHz)
3'b011
DIV_BY_8 Core Clock = CLOCK / 8 (6 MHz)
3'b100 - 3'b111 Not Used Reserved - Using these settings may cause functional damage to the B1411 device
OTP_CONFIG3[3]: Ena_VBUS_Sense
 Controls whether VBUS is sensed.
•Logic 0 = VBUS sense is not enabled (typically used in bus-powered mode)
•Logic 1 = VBUS sense is enabled (typically used in self-powered mode)
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