XR21B1411IL-0A-EB Datasheet, PDF (17/30 Pages) Exar Corporation – ENHANCED 1-CH FULL-SPEED USB UART

REV. 1.2.0
3.1.1.10
XR21B1411
ENHANCED 1-CH FULL-SPEED USB UART
ERROR_STATUS Register Description - Read-clear
This register reports any historical errors that have occurred on the line such as break, framing, parity and
overrun. Note that these errors cannot be directly associated with any bytes within the Rx FIFO. For
diagnostic purposes, the WIDE_MODE can be enabled. In this mode, errors are real time, i.e. are directly
associated with the current byte.
ERROR_STATUS[2:0]: Reserved
These bits are reserved. Any values read from these bits should be ignored.
ERROR_STATUS[3]: Break error
 Logic 0 = No break condition
 Logic 1 = A break condition has been detected (clears after read).
ERROR_STATUS[4]: Framing Error
 Logic 0 = No framing error
 Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected.
ERROR_STATUS[5]: Parity Error
 Logic 0 = No parity error
 Logic 1 = A parity error has been detected (clears after read).
ERROR_STATUS[6]: Overrun Error
 Logic 0 = No overrun error
 Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received.
ERROR_STATUS[7]: Break Status
 Logic 0 = Break condition is no longer present.
 Logic 1 = Break condition is currently being detected.
ERROR_STATUS[11:8]: Reserved
 These bits are reserved and should remain ’0’.
3.1.1.11 TX_BREAK Register Description (Read / Write)
Writing a value between 1 and 0xFFE to this register causes a break condition to be generated continuously
until the register is cleared. The register decrements at 1 ms intervals until the count is zero. If another non-
zero value, other than 0xFFF is written to the TX_BREAK register before the counter decrements to zero, the
decrement continues from the newly written value. A value of 0xFFF will cause the break condition to be
generated until a different value is written to the register.
If data is being shifted out of the TX pin, the data will be completely shifted out before the break condition is
generated.
Note that the break condition may be delayed by up to 1 ms following the write of the TX_BREAK register.
Additionally, the break condition may persist for up to 2 bit times after the counter has decremented to zero.
3.1.1.12 RS485_DELAY Register Description (Read / Write)
RS485_DELAY[3:0]: Turn-around delay
This is the number of bit times the B1411 waits before de-asserting the GPIO5/RTS#/RS485 pin when it is
configured for automatic RS-485 half-duplex control.
17