XR21B1411IL-0A-EB Datasheet, PDF (22/30 Pages) Exar Corporation – ENHANCED 1-CH FULL-SPEED USB UART

XR21B1411
ENHANCED 1-CH FULL-SPEED USB UART
REV. 1.2.0
LOOPBACK[1]: RTS_CTS
When this bit is set RTS is looped back to CTS.
 Logic 0 = Disable loopback.
 Logic 1 = Enable loopback.
LOOPBACK[2]: DTR_DSR
When this bit is set DTR is looped back to DSR.
 Logic 0 = Disable loopback.
 Logic 1 = Enable loopback.
LOOPBACK[11:3]: Reserved
These bits are reserved and should remain ’0’.
3.1.1.23 TX_FIFO_RESET (Write Only)
TX_FIFO_RESET[0]: Reset
 Write a ’1’ to reset the Tx FIFO, self-clearing.
TX_FIFO_RESET[11:1]: Reserved
These bits are reserved and should remain ’0’.
3.1.1.24 TX_FIFO_COUNT (Read Only)
TX_FIFO_COUNT[7:0]: Character Count
 Reports the number of characters currently in the Tx FIFO.
TX_FIFO_COUNT[11:8]: Reserved
These bits are reserved and should remain ’0’.
3.1.1.25 RX_FIFO_RESET (Write Only)
RX_FIFO_RESET[0]: Reset
 Write a ’1’ to reset the Rx FIFO, self-clearing.
RX_FIFO_RESET[11:1]: Reserved
These bits are reserved and should remain ’0’.
3.1.1.26 RX_FIFO_COUNT (Read Only)
RX_FIFO_COUNT[8:0]: Character Count
 Reports the number of characters currently in the Rx FIFO.
RX_FIFO_RESET[11:9]: Reserved
These bits are reserved and should remain ’0’.
3.1.1.27 RX_FIFO_LOW_LATENCY (Read / Write)
RX_FIFO_LOW_LATENCY[0]: Low Latency Enable
This register is automatically set to logic ’1’ for baud rates below 40961 bps.
 Logic 0 = Receive data is not from Rx FIFO until bMaxPacketSize (normally 64 bytes) or timeout (3
characters) has been reached. (Note: When the CDC-ACM driver is used, the bMaxPacketSize becomes
63 bytes.)
 Logic 1 = Receive data is forwarded from Rx FIFO immediately upon receipt.
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