XR21B1411IL-0A-EB Datasheet, PDF (13/30 Pages) Exar Corporation – ENHANCED 1-CH FULL-SPEED USB UART

XR21B1411
REV. 1.2.0
ENHANCED 1-CH FULL-SPEED USB UART
3.0 REGISTER SET DESCRIPTION
The internal register set of the B1411 controls the UART channel functionality, basic functionality of the FIFOs,
OTP controls, as well as registers associated with the processing of driver commands. These registers are
accessible via the USB interface using the XR_SET_REG and XR_GET_REG USB commands. Note that the
UART_ENABLE register should be used to disable the UART prior to any register write and re-enable the
UART following any single or sequence of register writes. Several exceptions are the GPIO_SET and
GPIO_CLEAR registers as well as the TX_BREAK and ERROR_STATUS registers. The UART does not need
to be disabled when writing these four registers.
3.1 B1411 Register Map
TABLE 5: B1411 REGISTERS
ADDRESS
REGISTER NAME
BIT-11
BIT-
10
BIT-9 BIT-8 BIT-7 BIT-6 BIT-5 BIT-4
BIT-3
BIT-2 BIT-1 BIT-0
0X20D CUSTOM_DRIVER ₀
0
0
0
0
0
0
0
0
0
0
ACTI
VE
0x216 CDC_ACM_-
FLOW_CONTROL
0
0
0
0
0
0
0
0
Half- Flow Control Mode
Duplex
Select
0x217 CDC_ACM_GPIO_-
XCVR
MODE
0
0
0
0
0
0
0
0 Enable
Mode Select
Polarity
0x218 CDC_ACM_GPIO_-
DIRECTION
0
0
0
0
0
0
GPIO GPIO GPIO GPIO GPIO GPIO
5
4
3
2
1
0
0x219 CDC_ACM_GPI-
O_INT_MASK
0
0
0
0
0
0
GPIO GPIO GPIO GPIO GPIO GPIO
5
4
3
2
1
0
0XC00 UART_ENABLE
0
0
0
0
0
0
0
0
0
0 RX TX
0xC06 FLOW_CONTROL ₀
0
0
0
0
0
0
0
Half- Flow Control Mode
Duplex
Select
0xC07 XON_CHAR
0
0
0
0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0xC08 XOFF_CHAR
0
0
0
0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0xC09 ERROR_STATUS
0
0
0
0
Break
Status
Over-
run
Error
Parity
Error
Fram-
ing
Error
Break
Error
0
0
0
0xC0A TX_BREAK
Bit-11 Bit-10 Bit-9 Bit-8 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0xC0B RS485_DELAY
0
0
0
0
0
0
0
0
Delay
0xC0C GPIO_MODE
0
0
0
0
0
0
0
0
RS485
Polarity
Mode Select
0xC0D GPIO_DIRECTION ₀
0
0
0
0
0
GPIO GPIO GPIO GPIO GPIO GPIO
5
4
3
2
1
0
0xC0E GPIO_SET
0
0
0
0
0
0
GPIO GPIO ^GPIO GPIO GPIO GPIO
5
4
3
2
1
0
0xC0F GPIO_CLEAR
0
0
0
0
0
0
GPIO GPIO ^GPIO GPIO GPIO GPIO
5
4
3
2
1
0
0xC10 GPIO_STATUS
0
0
0
0
0
0
GPIO GPIO GPIO GPIO GPIO GPIO
5
4
3
2
1
0
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