XR16L2550IM-F Datasheet, PDF (6/44 Pages) Exar Corporation – LOW VOLTAGE DUART WITH 16-BYTE FIFO

XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
REV. 1.1.3
1.0 PRODUCT DESCRIPTION
The XR16L2550 (L2550) provides serial asynchronous receive data synchronization, parallel-to-serial and
serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are
necessary for converting the serial data stream into parallel data that is required with digital data systems.
Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to
form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex especially when manufactured on a single integrated silicon
chip. The L2550 represents such an integration with greatly enhanced features. The L2550 is fabricated with
an advanced CMOS process.
Transmit and Receive FIFOs (16 Bytes each)
The L2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The L2550 is designed to work with high speed modems and
shared network environments, that require fast data processing time. Increased performance is realized in the
L2550 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This
means the external CPU will have to service the receive FIFO less than every 100 microseconds. However
with the 16 byte FIFO in the L2550, the data buffer will not require unloading/loading for 1.53 ms. This
increases the service interval giving the external CPU additional time for other applications and reducing the
overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is
uniquely provided for maximum data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
Data Rate
The L2550 is capable of operation up to 3.125 Mbps with a 50 MHz clock. With a crystal or external clock input
of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
Enhanced Features
The XR16L2550 integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate
generator with a prescaler of divide by 1 or 4, and data rate up to 4 Mbps at 5V.
The rich feature set of the L2550 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset, the L2550 is functionally and software compatible with the previous generation
ST16C2450 and ST16C2550.
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