XR16L2550IM-F Datasheet, PDF (3/44 Pages) Exar Corporation – LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.3
PIN DESCRIPTIONS
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
Pin Description
NAME
32-QFN 44-PLCC 48-TQFP
TYPE
PIN #
PIN #
PIN #
DESCRIPTION
DATA BUS INTERFACE
A2
18
29
26
I Address data lines [2:0]. These 3 address lines select one of the
A1
19
30
27
A0
20
31
28
internal registers in UART channel A/B during a data bus transac-
tion.
D7
2
9
3
IO Data bus lines [7:0] (bidirectional).
D6
1
8
2
D5
32
7
1
D4
31
6
48
D3
30
5
47
D2
29
4
46
D1
28
3
45
D0
27
2
44
IOR#
14
24
19
I Input/Output Read Strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal
register pointed to by the address lines [A2:A0]. The data byte is
placed on the data bus to allow the host processor to read it on
the rising edge.
IOW#
12
20
15
I Input/Output Write Strobe (active low). The falling edge instigates
an internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address
lines.
CSA#
7
16
10
I UART channel A select (active low) to enable UART channel A in
the device for data bus operation.
CSB#
8
17
11
I UART channel B select (active low) to enable UART channel B in
the device for data bus operation.
INTA
22
33
30
O UART channel A Interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set
to the active mode (active high) and OP2A# output to a logic 0
when MCR[3] is set to a logic 1. INTA is set to the three state
mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0
(Default).
INTB
21
32
29
O UART channel B Interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTB is set
to the active mode and OP2B# output to a logic 0 when MCR[3] is
set to a logic 1. INTB is set to the three state mode and OP2B# to
a logic 1 when MCR[3] is set to a logic 0 (Default).
TXRDYA#
-
1
43
O ^{UART channel A Transmitter Ready (active low). The output}
provides the TX FIFO/THR status for transmit channel A. If
it is not used, leave it unconnected.
RXRDYA#
-
34
31
O UART channel A Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channel A. If it is not
used, leave it unconnected.
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