XR16L2550IM-F Datasheet, PDF (24/44 Pages) Exar Corporation – LOW VOLTAGE DUART WITH 16-BYTE FIFO

XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
REV. 1.1.3
Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xoff/Special character is by detection of a Xoff or Special character.
• CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by
EFR bit-7.
• RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by
EFR bit-6.
4.4.2 Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptied or cleared from FIFO).
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
• Special character interrupt is cleared by a read to ISR or after the next character is received.
• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
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TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1
BIT-0
1
0
0
0
1
1
0 LSR (Receiver Line Status Register)
2
0
0
1
1
0
0 RXRDY (Receive Data Time-out)
3
0
0
0
1
0
0 RXRDY (Received Data Ready)
4
0
0
0
0
1
0 TXRDY (Transmit Ready)
5
0
0
0
0
0
0 MSR (Modem Status Register)
6
0
1
0
0
0
0 RXRDY (Received Xoff or Special character)
7
1
0
0
0
0
0 CTS#, RTS# change of state
-
0
0
0
0
0
1 None (default)
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