XR16M890_11 Datasheet, PDF (59/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

REV. 1.0.0
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 28. RECEIVE READY & INTERRUPT TIMING [FIFO MODE]
Start
Bit
RX
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
Stop
Bit
INT
T_SSR
RXRDY#
First Byte is
Received in
RX FIFO
T_SSI
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
T_RRI
T_RR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 29. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE]
TX FIFO
Empty
TX
(Unloading)
IER[1]
enabled
T_WTS
INT*
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T
T S D0:D7 T S D0:D7 T
T_SI
ISR is read
TX FIFO fills up
to trigger level
T_WRI
TX FIFO drops
below trigger level
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
TX FIFO
Empty
TXDMA#
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