XR16M890_11 Datasheet, PDF (5/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

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PIN DESCRIPTIONS
XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
Pin Description
NAME
QFN-32 QFN-40 TQFP-48
TYPE
PIN#
PIN#
PIN#
DESCRIPTION
DATA BUS INTERFACE - Intel/Motorola
16/68#
32
1
1
I _{Intel or Motorola Bus Select. This pin selects the 16 or 68 mode}
when VLIO_EN is a logic 0. In the VLIO mode (VLIO_EN is a logic
1), this pin becomes the SLEEP/PWRDN# pin in the QFN-32 pack-
age.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will oper-
ate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface. This pin does not have
an internal pull-up or pull-down resistor.
A2
29
38
46
I _{Address lines [2:0]. These 3 address lines select the internal regis-}
A1
30
39
47
ters in UART channel during a data bus transaction.
A0
31
40
48
In the VLIO bus mode (details on next page):
■ A2 becomes ENIR#
■ A1 becomes ENRS485# in the QFN-32 package
■ A1 is an unused input on the TQFP-48 and QFN-40
packages and should be connected to GND
■ A0 becomes LLA#
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
8
9
9
I/O _{Data bus lines [7:0] (bidirectional).}
7
8
8
6
7
7
5
6
6
In the VLIO bus mode, D7:D0 becomes AD7:AD0.
4
5
5
3
4
4
2
3
3
1
2
2
13
16
10
I _{When 16/68# pin is at logic 1, the Intel bus interface is selected and}
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input should be connected to VCC.
IOW#
14
17
11
I _{When 16/68# pin is at logic 1, it selects Intel bus interface and this}
(R/W#)
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
CS#
15
18
12
I _{This input is chip select (active low) to enable the device.}
5