XR16M890_11 Datasheet, PDF (53/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR16M890
REV. 1.0.0
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
AC ELECTRICAL CHARACTERISTICS
TA = -40^O TO +85^OC, VCC IS 1.62 TO 3.63V, 70 PF LOAD WHERE APPLICABLE
SYMBOL
T_AS
T_AH
T_CSL
T_LLA
T_RD
T_LLAR
T_LLAW
T_DY
T_RDV
T_DD
T_WR
T_DS
T_DH
T_WDO
T_MOD
T_RSI
T_SSI
T_RRI
T_SI
T_WTS
T_WTS
T_WRI
T_SSR
T_RR
T_WT
T_SRT
T_RST
Bclk
PARAMETER
LIMITS
1.8V ± 10%
MIN
MAX
LIMITS
2.5V ± 10%
MIN
MAX
LIMITS
3.3V ± 10%
MIN
MAX
UNIT
VLIO Data Bus Read/Write Timing
Address Setup Time
15
15
10
ns
Address Hold Time
5
5
5
ns
Delay from CS# to LLA#/IOR#/IOW#
0
0
0
ns
LLA# Strobe Width
10
10
10
ns
IOR# Strobe Width
50
45
40
ns
Delay from LLA# to IOR#
5
5
5
ns
Delay from LLA# to IOW#
5
5
5
ns
Read/Write Cycle Delay
50
45
40
ns
Data Access Time
45
40
35
ns
Data Disable Time
25
20
15
ns
IOW# Strobe Width
50
45
40
ns
Data Setup Time
15
15
15
ns
Data Hold Time
5
5
5
ns
Delay From IOW# To Output
Modem/Interrupt Timing
50
50
50
ns
Delay To Set Interrupt From MODEM Input
50
50
50
ns
Delay To Reset Interrupt From IOR#
50
50
50
ns
Delay From Stop To Set Interrupt
1
1
1 Bclk
Delay From IOR# To Reset Interrupt
45
45
45
ns
Delay From Start To Interrupt
45
45
45
ns
Delay From Initial IOW# To Transmit Start
(SHR[7:4] = 0x0)
Delay From Initial IOW# To Transmit Start
(SHR[7:4] = 0xF)
Delay From IOW# To Reset Interrupt
8
33
8
33
8
33 Bclk
8
48
8
48
8
48 Bclk
45
45
45
ns
Delay From Stop To Set RXRDY#
1
1
1 Bclk
Delay From IOR# To Reset RXRDY#
45
45
45
ns
Delay From IOW# To Set TXRDY#
45
45
45
ns
Delay From Center of Start To Reset TXRDY#
8
8
8 Bclk
Reset Pulse Width
40
40
40
ns
Baud Clock
16X or 8X or 4X of data rate
Hz
53