XR16M890_11 Datasheet, PDF (58/63 Pages) Exar Corporation – UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS

XR16M890
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
FIGURE 26. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE]
RX
INT
RXRDY#
Start
Bit
D0:D7
Stop
Bit
T_SSR
1 Byte
in RHR
T_SSR
Active
Data
Ready
T_RR
D0:D7
T_SSR
1 Byte
in RHR
T_SSR
Active
Data
Ready
T_RR
IOR#
(Reading data
out of RHR)
REV. 1.0.0
D0:D7
T_SSR
1 Byte
in RHR
T_SSR
Active
Data
Ready
T_RR
RXNFM
FIGURE 27. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE]
TX
(Unloading)
T_WTS
IER[1] enabled
Start
Bit
D0:D7
Stop
Bit
ISR is read
INT*
T_WRI
TXRDY#
T_WRI
T_SRT
D0:D7
ISR is read
T_SRT
T_WRI
D0:D7
ISR is read
T_SRT
T_WT
T_WT
T_WT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
58