XR16V698 Datasheet, PDF (58/58 Pages) Exar Corporation – 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO

XR16V698
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
REV. 1.0.3
3.1.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
00-00).............................................................................................................................................................................. 26
3.1.2.1 TIMERMSB [7:0] AND TIMERLSB [7:0] ............................................................................................................. 26
3.1.2.2 TIMER [7:0] RESERVED....................................................................................................................................... 26
3.1.2.3 TIMERCNTL [7:0] REGISTER .............................................................................................................................. 26
TABLE 10: TIMER CONTROL COMMANDS ....................................................................................................................................... 27
TIMER OPERATION ................................................................................................................................................ 27
FIGURE 14. TIMER/COUNTER CIRCUIT............................................................................................................................................. 27
FIGURE 15. INTERRUPT OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES................................................................................. 28
3.1.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 28
3.1.4 4XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 28
3.1.5 RESET [7:0] (DEFAULT 0X00) ..................................................................................................................................... 29
3.1.6 SLEEP [7:0] (DEFAULT 0X00) ..................................................................................................................................... 29
3.1.7 DEVICE IDENTIFICATION AND REVISION ................................................................................................................. 29
3.1.7.1 DVID [7:0] (DEFAULT 0X68) ................................................................................................................................. 29
3.1.7.2 DREV [7:0] (DEFAULT (0X01) .............................................................................................................................. 29
3.1.8 REGB [7:0] (DEFAULT 0X00) ...................................................................................................................................... 29
3.2 UART CHANNEL CONFIGURATION REGISTERS .......................................................................................... 30
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS ............................................................................................................... 30
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ........................ 31
4.0 INTERNAL REGISTER DESCRIPTIONS............................................................................................... 32
4.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 32
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY................................................................................ 32
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 32
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 32
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 32
4.4 INTERRUPT STATUS REGISTER (ISR) - READ ONLY................................................................................... 34
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 34
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 34
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 35
4.5 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 35
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 36
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 36
TABLE 15: PARITY PROGRAMMING .................................................................................................................................................. 37
4.7 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 38
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 39
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 40
4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY .................................................................................... 41
TABLE 16: AUTO RS-485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................ 42
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 43
4.12 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE............................................................................ 43
4.13 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 44
TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 45
4.14 XOFF1, XOFF2, XON1 AND XON2 REGISTERS - WRITE ONLY.................................................................. 45
4.15 XCHAR REGISTER - READ ONLY ................................................................................................................ 46
TABLE 18: UART RESET CONDITIONS ............................................................................................................................................ 47
ABSOLUTE MAXIMUM RATINGS.................................................................................. 48
ELECTRICAL CHARACTERISTICS ............................................................................... 48
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 48
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 49
FIGURE 16. 16 MODE (INTEL) DATA BUS READ AND WRITE TIMING ................................................................................................. 51
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ AND WRITE TIMING ........................................................................................ 52
FIGURE 18. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 53
FIGURE 19. RECEIVE INTERRUPT TIMING [NON-FIFO MODE]........................................................................................................... 53
FIGURE 20. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]......................................................................................................... 54
FIGURE 21. RECEIVE INTERRUPT TIMING [FIFO MODE]................................................................................................................... 54
FIGURE 22. TRANSMIT INTERRUPT TIMING [FIFO MODE]................................................................................................................. 54
PACKAGE DIMENSIONS................................................................................................ 55
REVISION HISTORY...................................................................................................................................... 56
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