XR16V698 Datasheet, PDF (35/58 Pages) Exar Corporation – 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO

REV. 1.0.3
]
PRIORITY
LEVEL BIT-5
1
0
2
0
3
0
4
0
5
0
6
0
7
1
X
0
XR16V698
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT
BIT-4 BIT-3 BIT-2 BIT-1
BIT-0
0
0
1
1
0 LSR (Receiver Line Status Register)
0
0
1
0
0 RXRDY (Received Data Ready)
0
1
1
0
0 RXRDY (Receive Data Time-out)
0
0
0
1
0 TXRDY (Transmitter Holding Register Empty)
0
0
0
0
0 MSR (Modem Status Register)
1
0
0
0
0 RXRDY (Received Xon/Xoff or Special character)
0
0
0
0
0 CTS#/DSR#, RTS#/DTR# change of state
0
0
0
0
1 None (default) or wake-up indicator
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 13). See “Section
4.4.1, Interrupt Generation:” on page 34 and “Section 4.4.2, Interrupt Clearing:” on page 34 for details.
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending. (default condition)
4.5 FIFO Control Register (FCR) - Write Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 14 shows the complete selections.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last re-load. Table 14 below shows the selections.
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