XR16C854D Datasheet, PDF (5/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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REV. 3.0
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Pin Description
NAME
64-TQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
CSD#
42
54
68
I When 16/68# pin is at logic 1, this input is chip select D (active low)
(N.C.)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used.
Motorola bus interface is not available on the 64 pin package.
INTA
6
(IRQ#)
15
12
O When 16/68# pin is at logic 1 for Intel bus interface, this ouput
(OD) ^{becomes channel A interrupt output. The output state is defined}
by the user and through the software setting of MCR[3]. INTA is set
to the active mode when MCR[3] is set to a logic 1. INTA is set to
the three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
Motorola bus interface is not available on the 64 pin package.
INTB
12
21
18
O When 16/68# pin is at logic 1 for Intel bus interface, these ouputs
INTC
37
49
63
INTD
43
55
69
(N.C.)
become the interrupt outputs for channels B, C, and D. The output
state is defined by the user through the software setting of MCR[3].
The interrupt outputs are set to the active mode when MCR[3] is
set to a logic 1 and are set to the three state mode when MCR[3] is
set to a logic 0 (default). See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.
Motorola bus interface is not available on the 64 pin package.
INTSEL
-
TXRDYA#
-
TXRDYB#
-
TXRDYC#
-
TXRDYD#
-
65
87
I Interrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-
D pins or override MCR bit-3 and enable the interrupt outputs.
Interrupt outputs are enabled continuously by making this pin a
logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and
disable the interrupt output pins. In this mode, MCR bit-3 is set to a
logic 1 to enable the continuous output. See MCR bit-3 description
for full detail. This pin must be at logic 0 in the Motorola bus inter-
face mode. Due to pin limitations on 64 pin packages, this pin is
not available. To cover this limitation, two 64 pin TQFP packages
versions are offered. The XR16C854D operates in the continuous
interrupt enable mode by bonding this pin to VCC internally.
-
5
O ^{UART channels A-D Transmitter Ready (active low). The outputs}
-
25
-
56
provide the TX FIFO/THR status for transmit channels A-D. See
Table 5 on page 13. If these outputs are unused, leave them
unconnected.
-
81
RXRDYA#
-
RXRDYB#
-
RXRDYC#
-
RXRDYD#
-
-
100
O UART channels A-D Receiver Ready (active low). This output pro-
-
31
-
50
-
82
vides the RX FIFO/RHR status for receive channels A-D. See
Table 5 on page 13. If these outputs are unused, leave them
unconnected.
TXRDY#
-
39
45
O Transmitter Ready (active low). This output is a logically wire-
ORed status of TXRDY# A-D. See Table 5 on page 13. If this out-
put is unused, leave it unconnected.
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