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XR16C854D Datasheet, PDF (31/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO | |||
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REV. 3.0
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 12 for parity selection summary below.
⢠Logic 0 = No parity.
⢠Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
⢠Logic 0 = ODD Parity is generated by forcing an odd number of logic 1âs in the transmitted character. The
receiver must be programmed to check the same format (default).
⢠Logic 1 = EVEN Parity is generated by forcing an even number of logic 1âs in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
⢠LCR BIT-5 = logic 0, parity is not forced (default).
⢠LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
⢠LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 12: PARITY SELECTION
LCR BIT-5
X
0
0
1
1
LCR BIT-4
X
0
1
0
1
LCR BIT-3
0
1
1
1
1
PARITY SELECTION
No parity
Odd parity
Even parity
Force parity to mark, â1â
Forced parity to space, â0â
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
âspaceâ, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
⢠Logic 0 = No TX break condition (default).
⢠Logic 1 = Forces the transmitter output (TX) to a âspaceâ, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
⢠Logic 0 = Data registers are selected (default).
⢠Logic 1 = Divisor latch registers are selected.
31
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