XR16C854D Datasheet, PDF (20/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
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REV. 3.0
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some
infrared modules on the market which indicate a logic 0 by a light pulse. So the 854 has a provision to invert the
input polarity to accomodate this. In this case user can enable FCTR bit-2 to invert the input signal.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
C h a ra cte r
Data Bits
TX Data 0 ¹ 0 ¹ 0 0 ^{1 1} 0 ¹
Transm it
IR Pulse
(TX Pin)
Bit Tim e
3/16 Bit Tim e
1/2 Bit Tim e
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
RX Data
0 1 0 1 0 0 11 0 1
Data Bits
Character
IRdecoder-1
2.19 Sleep Mode with Auto Wake-Up
The 854 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used.
All of these conditions must be satisfied for the 854 to enter sleep mode:
s no interrupts pending for all four channels of the 854 (ISR bit-0 = 1)
s sleep mode of all four channels are enabled (IER bit-4 = 1)
s modem inputs are not toggling (MSR bits 0-3 = 0)
s RX input pins are idling at a logic 1
The 854 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no
clock output as an indication that the device has entered the sleep mode.
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