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XR21B1420IL28-0A Datasheet, PDF (48/60 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed USB UART | |||
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Bit
4:2
1:0
Default
Description
0
SEL
000: Assert logic â1â during SUSPEND or USB BUS_RESET else logic â0â
001: Assert logic â1â during SUSPEND else logic â0â
010: Assert logic â1â during LOW_PWR else logic â0â
011: Assert logic â1â during USB BUS_RESET else logic â0â
100: Assert logic â1â during SUSPEND or USB BUS_RESET else logic â0â
101: Assert logic â0â during SUSPEND else logic â1â
110: Assert logic â0â during LOW_PWR else logic â1â
111: Assert logic â0â during USB BUS_RESET else logic â1â
0
CTRL
00: Invalid, do not use
01: Output, open drain
10: Output, push-pull
11: Invalid, do not use
PIN_CFG_USB_STAT2 (0x020) - Read/Write OTP
Controls the configuration of the USB_STAT2 pin during suspend state
Bit
7:5
4:2
1:0
Default
Description
0
Reserved
These bits are reserved and should be written as â0â.
0
SEL
000: Assert logic â0â during SUSPEND or USB BUS_RESET else logic â1â
001: Assert logic â1â during SUSPEND else logic â0â
010: Assert logic â1â during LOW_PWR else logic â0â
011: Assert logic â1â during USB BUS_RESET else logic â0â
100: Assert logic â0â during SUSPEND or USB BUS_RESET else logic â1â
101: Assert logic â0â during SUSPEND else logic â1â
110: Assert logic â0â during LOW_PWR else logic â1â
111: Assert logic â0â during USB BUS_RESET else logic â1â
0
CTRL
00: Invalid, do not use
01: Output, open drain
10: Output, push-pull
11: Invalid, do not use
XR21B1420
© 2014 Exar Corporation
48 / 60
exar.com/XR21B1420
Rev 1A
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