XR21B1420IL28-0A Datasheet, PDF (11/60 Pages) Exar Corporation – Enhanced 1-Ch Full-Speed USB UART

XR21B1420
parity is selected, the TX FIFO contains 8 bits data and the parity bit is automatically generated and transmitted. If 9 bit data
is selected, parity cannot be generated. The 9th bit will not be transmitted unless the wide mode is enabled.
Wide Mode Transmit
When both 9 bit data and wide mode are enabled, two bytes of data will be written into the TX FIFO. The first byte is the first
8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte is bit-8 of the 9-bit data. The data that is transmitted on the TX
pin is as follows: start bit, 9-bit data, stop bit. Wide mode may be enabled using the TX_WIDE_MODE and RX_WIDE_-
MODE registers.
Receiver
The receiver consists of a 512-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the
RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host by in response to a bulk-in request.
Depending on the mode, error / status information for that data character may or may not be stored in the RX FIFO with the
data.
Normal receive operation with 5, 6, 7 or 8-bit data
Received data is stored in the RX FIFO. Any parity, framing or overrun error or break status information related to the data
is discarded. The receive data format is shown in Figure 4.
7, 8, or 9 bit data
1^ST byte 7 6 5 4 3 2 1 0 _{7 = ‘0’ in 7 bit mode}
Figure 4: Receive Data Format
Normal receive operation with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun error or break
status information related to the data is discarded.
Wide mode receive operation with 5, 6, 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received data. The sec-
ond byte consists of the error bits and break status. Wide mode receive data format is shown in Figure 5.
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