XRS10L120_09 Datasheet, PDF (4/36 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER

EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
2.0 PIN DESCRIPTIONS
TABLE 1: XRS10L120 PIN DESCRIPTIONS
Pin Name
Pin Number I/O
64 QFN
Type
DESCRIPTION
REV. 1.06
SOTP0/SOTN0
SOTP1/SOTN1
SORP0/SORN0
SORP1/SORN1
SITP/SITN
SIRP/SIRN
CMU_REFP/
CMU_REFN
XOD
XOG
MDC
MDIO
TCK
TDI
TDO
TMS
TRST
RBIAS
RESETB
PWRDNB
DATA INTERFACE
45, 46
34, 33
CML
AC
O
Coupled Serial ATA Output Transmitters. These ports communicate
from the XRS10L120 to downstream devices
42, 43
37, 36
I
Serial ATA Input Receivers. These ports receive signals from
downstream devices
62, 63
O
Serial ATA Output Transmitters. These ports communicate
from the XRS10L120 to upstream hosts.
59, 60
I
Serial ATA Input Receivers. These ports receive signals from
upstream hosts.
CLOCK INTERFACE
25, 26
CML
AC
Coupled
Reference clock input
22
O
Analog Crystal oscillator output
23
I
Analog Crystal oscillator input, 1.26V max
MDIO INTERFACE SIGNALS
7
I
LVCMOS MDIO clock input, +3.3V LVCMOS
9
I/O LVCMOS MDIO data port, +3.3V LVCMOS. Open drain
JTAG Interface Signals
1
I
LVCMOS JTAG test clock, +3.3V LVCMOS
4
I
JTAG test data in, +3.3V LVCMOS
3
O
JTAG test data out, +3.3V LVCMOS. Open drain. If used to
daisy chain JTAG devices, pull up externally using 3.3KOhm
resistor.
2
I
JTAG mode select, +3.3V LVCMOS
5
I
JTAG test reset, +3.3V LVCMOS. Pull low externally using
3.3KOhm resistor for normal operation of the device
GENERAL CONTROL AND CONFIGURATION SIGNALS (CMOS)
28
I
Analog Connection point for calibration termination resistor.
50
I
LVCMOS Active low reset pin, +3.3V LVCMOS.
31
I
LVCMOS Active low power down signal for chip, +3.3V LVCMOS.
4