XRS10L120_09 Datasheet, PDF (16/36 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER

EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
TABLE 3: SERIAL ATA LINK SPECIFICATIONS
NAME
DESCRIPTION
MIN.
NOM
MAX
UNITS
t_BIT,XS
Bit Time
670
-
333
ps
J_XR1
Input Jitter Tolerance Mask at signal crossover
0.32
-
-
UI
J_XR1,DJ Deterministic jitter tolerance at signal crossover
0.18
-
-
UI
J_XT1
Output jitter mask at signal crossover
-
-
0.15
UI
J_XT1,DJ Deterministic output jitter at signal crossover
-
-
0.07
UI
t_R/t_F
Input signal rise/fall times (20% - 80%)
0.2
-
0.46
UI
t_QR/t_QF Output signal rise/fall times (20% - 80%)
0.2
-
0.41
UI
t_TOL,RX^{1 RX to sysclock frequency offset tolerance}
-5350
0
350
ppm
V_IN
Input swing, differential peak-peak
175
-
1600
mV
V_SW²
Output swing, differential peak-peak
800
-
1200
mV
V_IN,IDLE No swing detection threshold
65
120
155
mV
R_IN,DIFF Differential mode input resistance
85
100
115
Ω
R_IN,CM^{3 Common mode input resistance}
40
50
60
Ω
R_IN,OFF Common mode input resistance, no power
200
-
-
kΩ
R_IN,XS Output termination resistance
40
50
60
Ω
S_11,IN,DIFF Differential input return loss, 50MHz - 1.5GHz
12
-
-
dB
S_11,IN,CM Common mode input return loss 50MHz-1.5GHz
6
-
-
dB
S_22,OUT,DIFF Differential output return loss 50MHz-1.5GHz
12
-
-
dB
S_22,OUT,CM Common mode output return loss 50MHz-1.5GHz
6
-
-
dB
t_S,REG Setup time for register port
1.5
-
-
ns
t_H,REG Hold time for register port
1.5
-
-
ns
t_Q,REG Clock to Q time for register port
0
-
2
ns
t_CYC,REG Register port clock cycle time
10
-
-
ns
t_HI,REG R register port clock high time
4
-
-
ns
t_LO,REG Register port clock low time
4
-
-
ns
t_RF,REG Register port input rise/fall time
-
-
0.5
ns
NOTES:
1. This value includes 0.5% downspread Spread Spectrum clocking, plus 350ppm tolerance around the center
frequency.
2. This is measured at the package ball and does not include any board or connector loss.
3. This value can be as low as 5Ω during power on.
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