XRS10L120_09 Datasheet, PDF (21/36 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER

EXSTOR XRS10L120
REV. 1.06
SERIAL ATA II: PORT MULTIPLIER
5.0 REGISTERS DESCRIPTION
The XRS10L120 provides a variety of registers for the purpose of device configuration, testing and monitoring.
These registers are accessed through the MDIO interface, outlined in “Section 4.3, MDIO Interface” on
page 17. Operational registers available to the customer are given below. Note that all other addres space
should be left unmodified in order to ensure proper behaviour of the device.
5.1 Register Overview
The XRS10L120 port address is hardwired to 0; this field should be set to 0 in all packets.The XRS10L120
contains three identical instantiations of a dual Serial ATA PHY macro. A common set of registers exists within
each of these macros, and are outlined in “Section 5.2, Macro Registers” on page 22. MDIO device
designations 1-3 are used for each of these three macros as shown in Table 7. Registers relating to the
XRS10L120 as a whole are outlined in “Section 5.3, XRS10L120 Device Generic Registers” on page 27
and make use of MDIO device 0.
TABLE 7: MDIO DEVICE DESIGNATIONS
MDIO DEVICE DESIGNATION
MACRO
RELEVANT PINS
0
XRS10L120 Device Generic Registers
N/A
1
Serial ATA Host Interface Macro (Lane 0)
SI
2
Serial ATA Devoce Interface Macro 0
SO0, SO1
The XRS10L120 registers are arranged as 8-bit fields with 8-bit addresses. These are mapped into the 16-bit
MDIO address and data fields by setting the most significant byte of each to be 0. An example mapping from a
macro address/data combination to an MDIO address & data combination is shown in Table 8.
TABLE 8: MDIO ADDRESSING
MACRO ADDRESS
MACRO DATA
MDIO ADDRESS
MDIO DATA
0x40
abcde
0x0040
00000000000abcde
NOTE: The unused upper 3 bits in FBDIV are also set to 0 during MDIO writes and are undefined during MDIO reads.
In the description of each register field, there is an entry describing its read/write status. This may fall into one
of the following categories:
• R/W- register field is read/write
• RO - register field is read only
• LL - Latching Low - Used with bits that monitor some state internal to the XRS10L120. When the condition
for the bit to go low is reached, the bit stays low until the next time it is read. Once it is read, its value reverts
to the cur-rent state of the condition it monitors.
• LH - Latching High - When the condition for the bit to go high is reached, the bit stays high until the next time
it is read. Once it is read, its value reverts to the current state of the condition it monitors.
• SC - When an SC bit is set, some action is initiated; once the action is complete, the bit is cleared.
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