XRS10L120_09 Datasheet, PDF (22/36 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER

EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
5.2 Macro Registers
The registers outlined in this section are common to each of the two Serial ATA dual PHY macros as described
in the previous section. As such, each listed register is present in each of the 1 and 2 MDIO register spaces,
and will perform the stated function on the specified Serial ATA lane.
The registers within each dual PHY macro are split into the following sections:
Transmit/Receive lane 0 registers:
Address range 000*****
Transmit/Receive lane 1 registers:
Address range 001*****
PLL registers:
Address range 010*****
Bias generator registers:
Address range 011*****
ADDRESS
HEX
N.0000
N.0020
N.0001
N.0021
TABLE 9: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2)
BIT(S)
NAME
R/W DEFAULT
DESCRPTION
7
Reserved
R/W
0 DO NOT MODIFY
6
SATAPCIEXB_G1
R/W
0 Tx output swing booster bit (Gen 1)
0 = boost swing by 15%
1 = nominal swing
5:1
Reserved
R/W
00001 DO NOT MODIFY
0
SATAPCIEXB_G2
R/W
0 Tx output swing booster bit (Gen 2)
0 = boost swing by 15%
1 = nominal swing
7:3
Reserved
R/W
00000 DO NOT MODIFY
2:0
Transmit_Eq0[2:0]
R/W
Transmit_Eq1[2:0]
011 Transmit pre-emphasis control
000 = 0% transmit preemphasis
001 = 6.5% transmit preemphasis
010 = 13% transmit preemphasis
011 = 19.5% transmit preemphasis
100 = 26% transmit preemphasis
101 = 32.5% transmit preemphasis
110 = 39% transmit preemphasis
111 = 45.5% transmit preemphasis
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