XRS10L120_09 Datasheet, PDF (12/36 Pages) Exar Corporation – SERIAL ATA II: PORT MULTIPLIER

EXSTOR XRS10L120
SERIAL ATA II: PORT MULTIPLIER
REV. 1.06
3.5 Clocking
The XRS10L120 allows the use of either an external reference clock or of a low cost crystal oscillator to act as
a reference clock. Separate device inputs are available for each approach, with full rate reference clock inputs
provided on pins CMU_REFP and CMU_REFN, and crystal oscillator inputs provided on pins XOD and XOG.
Supported data rates and their appropriate PLL divide factors are outlined in Table 2.
TABLE 2: PLL DIVIDE FACTORS
MODE
SYSCLK
/REF
DINCLK
SERIAL
DATA
/FB
RXCLK
CLOCK
RATE
SATA Gen. 2
25MHz
1
60
300MHz
1.5GHz
3.0Gbps*
SATA Gen. 2
75MHz
1
20
300MHz
1.5GHz
3.0Gbps*
SATA Gen. 2
100MHz
2
30
300MHz
1.5GHz
3.0Gbps*
SATA Gen. 2
150MHz
1
10
300MHz
1.5GHz
3.0Gbps*
NOTE: * All link start with 3.0Gbps, then negotiate down to 1.5Gbps for SATA Generation 1 devices.
3.5.1 Spread Spectrum Clocking
The XRS10L120 provides full support for receipt and generation of signals that have been configured for
Spread Spectrum Clocking (SSC) support. The spread technique is implemented by down-spreading the data
rate by 0.5% as a means of reducing EMI. Generation of the down-spread clock is performed within the
XRS10L120. An example of the resultant spectral fundamental frequency before and after SSC can be seen in
Figure 9.
FIGURE 9. SPREAD SPECTRUM CLOCKING
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