XRD9825 Datasheet, PDF (4/33 Pages) Exar Corporation – 16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9825
ELECTRICAL CHARACTERISTICS
Test Conditions: AV_DD=DV_DD=5V, ADCCLK=12MHz, 50% Duty Cycle, T_A=25°C unless otherwise specified.
Symbol Parameter
Min.
Power Supplies
AV
Analog Power Supply
3.0
DD
DV_DD
Digital I/O Power Supply
3.0
I
Supply Current
25
DD
IDD_PD
Power Down Power Supply Current
ADC Specifications
RES
Resolution
16
F
Maximum Sampling Rate
12
s
DNL
Differential Non-Linearity
V_RB
∆V_REF
R
L
Bottom Reference Voltage
Differential Reference Voltage
(V_RT - V_RB)
Ladder Resistance
PGA & Offset DAC Specifications
PGARES
PGAG_MIN
PGAG
MAX
PGAGD
V_BLACK
DACRES
OFF_MIN
OFF_MAX
OFF
MIN
OFF_MAX
OFF∆
PGA Resolution
Minimum Gain
Maximum Gain
Gain Adjustment Step Size
Black Level Input Range
Offset DAC Resolution
Minimum Offset Adjustment
Maximum Offset Adjustment
Minimum Offset Adjustment
Maximum Offset Adjustment
Offset Adjustment Step Size
0.3
300
6
0.950
9.5
-100
8
-250
+500
-450
+350
Typ. Max. Unit Conditions
3.3
5.5
V (Note 2)
3.3
5.5
V DV_DD < AV_DD
40
60
mA V =5V
DD
50
µA V_DD=5V
-0.7, +1.5
-0.8, +2.0
AV_DD/10
0.67AV_DD
Bits
MSPS
LSB ADCCLK = 10MHz
ADCCLK = 12MHz
V
V
600
780
Ω
1.0
10.0
0.14
-200
+600
-400
+400
3.125
1.050
10.50
500
-150
+700
-350
+450
Bits
V/V
V/V
V/V
mV DC Configuration
Bits
mV Mode 111, D5=0 (Note 1)
mV Mode 111, D5=0
mV Mode 111, D5=1 (Note 1)
mV Mode 111, D5=1
mV
Note 1: The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate
for any additional offset introduced by the XRD9825 Buffer/PGA internally.
Note 2: It is not recommended to operate the part between 3.6V and 4.4V.
Rev. 1.00
4