XRD9825 Datasheet, PDF (15/33 Pages) Exar Corporation – 16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9825
CIS
ADCCLK
DB ^[5:0]
[11:6]
CLAMP
CIS Mode Timing -- AC Coupled
(CLAMP enabled)
Pixel N-1
Pixel N
Pixel N+1
tap
tap
tckpd
tckhw tcklw
tclpw
tdv tdv
N-8 N-8 N-7
MSB _LSB MSB
N-7 N-6
LSB ^MSB
N-6 _{N-5 N-5}
LSB ^MSB LSB
Note: There is an 8 clock latency for the output
Figure 9. Timing Diagram for Figure 8
Rev. 1.00
ADCCLK
↓
↑
HI
LO
CLAMP
HI
LO
Events
ADC Sample & PGA Start Track of next Pixel
MSB Data Out (8 Upper Bits)
LSB Data Out (8 Lower Bits)
ADC Track PGA Output
ADC Hold/Convert
Table 3.
Events
PGA Tracks V_CLAMP & C_EXT is Charged to
V_BLACK - V_CLAMP, which is equal to V_BLACK
PGA Tracks VIN_PP
Table 4.
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