XRD9825 Datasheet, PDF (24/33 Pages) Exar Corporation – 16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9825
RED
N Pixel
PIXEL-BY-PIXEL 3 CHANNEL CCD -- AC Coupled
(CLAMP Enabled)
N+1 Pixel
GRN
BLU
N Pixel
N Pixel
tclp=10ns
N+1 Pixel
N+1 Pixel
tclp=10ns
ADCCLK
CLAMP
TRACK
RED (N)
trars
CONVERT
RED (N)
TRACK
GRN (N)
CONVERT
GRN (N)
CLAMP
TRACK
BLU (N)
CONVERT
BLU (N)
TRACK
RED (N+1)
Simultaneous
Sample
tap
CONVERT
RED (N+1)
DATA
SYNCH
tsypw
tdv
tdv
tdv
RED (N-6)
MSB
RED (N-6)
LSB
GRN (N-6)
MSB
tsa
tdv
GRN (N-6)
LSB
BLU (N-6)
MSB
tdv
BLU (N-6)
LSB
Note: There is an 8 clock latency at the output.
Figure 18. Timing Diagram for Figure 17
ADCCLK
3rd ↓
All ↓
↑
HI
LO
CLAMP
HI
LO
SYNCH
HI
LO
Events
Simultaneous RED/GRN/BLU Sample Every 3rd CLK.
Convert RED, S/H GRN, S/H BLU.
MSB Data Out (8 upper bits)
LSB Data Out (8 lower bits)
ADC Track PGA Output
ADC Hold/Convert
Events
Internal Clamp Enabled
Internal RED/GRN/BLU Tracking Enabled
Events
Reset Internal Mux to Red, Output Bus is Tri-stated
Increment Mux Color on Falling Edge of ADCCLK
Table 5.
Rev. 1.00
24