XRD9825 Datasheet, PDF (29/33 Pages) Exar Corporation – 16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9825
Control Registers
Function
(Register
S2/S1/S0)
D7
Red Gain
(000)
Red Offset
(001)
Grn Gain
(010)
Grn Offset
(011)
Blu Gain
(100)
Blu Offset
(101)
Mode
(110)
G5
(MSB)
O7
(MSB)
G5
(MSB)
O7
(MSB)
G5
(MSB)
O7
(MSB)
POWER
DOWN
0: NORMAL
1:
POWER
DOWN
Mode
&Test
(111)
TEST5
0:NOT USED
1:NORMAL
D6
D5
G4
G3
O6
O5
G4
G3
O6
O5
G4
G3
O6
O5
DIGITAL
V_RT
RESET
0: NO RESET 0: INTERNAL
1:RESET
(REGISTERS
ARE RESET TO
POWER-UP
STATES)
1: EXTERNAL
OUTPUT
DISABLE
0:OUTPUTS
ENABLED
1:OUTPUTS
DISABLED
OFFSET
DAC
RANGE
0:-200mV to
+600mV
1:-400mV to
+400mV
D4
D3
D2
D1
D0
Power-up
State
(Note 1)
G2
G1
G0
X
X
000000XX
(LSB)
O4
O3
O2
O1
O0
01000000
(LSB)
G2
G1
G0
X
X
000000XX
(LSB)
O4
O3
O2
O1
O0
01000000
(LSB)
G2
G1
G0
X
X
000000XX
(LSB)
O4
O3
O2
O1
O0
01000000
(LSB)
INPUT DC
REFERENCE
(V )
DCREF
0: INTERNAL
(V =AGND)
DCREF
1: EXTERNAL
(V =V )
DCREF DCEXT
DC/AC
0: DC
1: AC
SIGNAL
POLARITY
SIGNAL
CONFIGURATION
00000000
0: Non-
Inverted
(CIS)
1: Inverted
(CCD/CIS)
00: Single-Channel
RED input/gain/offset
01: Single-Channel
RED input
RED/GRN/BLU
gain/offset cycle
pixel-by-pixel
10: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
INTERNAL CIS
REFERENCE
CIRCUIT
TEST4
TEST3
TEST2
TEST1
00000000
0:NORMAL
0: TEST4 0: TEST3 0: TEST2 0:NORMAL
DISABLED DISABLED DISABLED
1:REFERENCE
CIRCUIT
ENABLED
1: OUTPUT 1: OUTPUT
OF BUFFER OF PGA
TIED TO TIED TO
BLU
VDCEXT
1: INPUT
OF ADC
TIED TO
GRN
1: TEST1
ENABLED
Rev. 1.00
29