XR17D158IV-F Datasheet, PDF (38/73 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
xr
REV. 1.2.2
5.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING
The 8 sets of UART configuration registers are decoded using address lines A8 to A11 as shown below.
Address lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with
EXAR enhanced feature registers located on the upper 8 addresses. Addresses 0x080 to 0x093 comprise the
Device Configuration Registers and they reside in Channel 0’s space.
A11 A10 A9
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A8 ^{UART CHANNEL}
SELECTION
0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
.
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS
ADDRESS
REGISTER
READ/WRITE
A3 A2 A1 A0
16550 COMPATIBLE REGISTERS
0 0 0 0 RHR - Receive Holding Register
Read-only
0 0 0 0 THR - Transmit Holding Register
Write-only
0 0 0 0 DLL - Div Latch Low
Read/Write
0 0 0 1 DLM - Div Latch High
Read/Write
0 0 0 1 IER - Interrupt Enable Register
Read/Write
0 0 1 0 ISR - Interrupt Status Register
Read-only
0 0 1 0 FCR - FIFO Control Register
Write-only
0 0 1 1 LCR - Line Control Register
Read/Write
0 1 0 0 MCR - Modem Control Register
Read/Write
0 1 0 1 LSR - Line Status Register
Read-only
0 1 1 0 MSR - Modem Status Register
Read-only
0 1 1 0 RS485 Turn-Around Delay Register
Write-only
0 1 1 1 SPR - Scratch Pad Register
Read/Write
ENHANCED REGISTERS
1 0 0 0 FCTR - Feature Control Register
Read/Write
1 0 0 1 EFR - Enhanced Function Register
Read/Write
1 0 1 0 TXCNT - Transmit FIFO Level Counter
Read-only
COMMENTS
LCR[7] = 0
LCR[7] = 0
LCR[7] = 1
LCR[7] = 1
LCR[7] = 0
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