XR17D158IV-F Datasheet, PDF (34/73 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
5.3.3 Receiver Operation with FIFO
FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
xr
REV. 1.2.2
16X or 8X Sampling
Clock (8XMODE Reg.)
64 bytes by 11-
bit wide FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
Receive Data
FIFO
(64-byte)
Data falls to 40 ^{RTS#/DTR# re-asserts when data falls below}
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
FIFO Trigger=48 ^{RHR Interrupt (ISR bit-2) is programmed}
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
Receive
Data
Data fills to 56 ^{RTS#/DTR# de-asserts when data fills above}
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RXFIFO1
5.4 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver
FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request the remote unit to suspend/
restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart the local transmitter.
The auto RTS/CTS or DTR/DSR flow control features are individually selected to fit specific application
requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS or DTR/DSR control
signals.
TABLE 11: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION
MCR BIT-2
EFR BIT-7
EFR BIT-6
HARDWARE FLOW CONTROL SELECTION
0
1
X
Auto CTS Flow Control Enabled
0
X
1
Auto RTS Flow Control Enabled
1
1
X
Auto DSR Flow Control Enabled
1
X
1
Auto DTR Flow Control Enabled
X
0
0
No Hardware Flow Control
Auto RTS flow control must be started by asserting the RTS# output pin LOW (MCR bit-1 = 1). Similarly, Auto
DTR flow control must be started by asserting the DTR# output pin LOW (MCR bit-0 = 1). Figure 16 shows in
detail how automatic hardware flow control works.
34