XR17D158IV-F Datasheet, PDF (11/73 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART

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REV. 1.2.2
XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
2.0 XR17D158 REGISTERS
The XR17D158 UART has three different sets of registers as shown in Figure 5. The PCI local bus
configuration space registers are for plug-and-play auto-configuration when connecting the device to a the PCI
bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI
local bus specification. The second register set is the device configuration registers that are accessible directly
from the PCI bus for programming general operating conditions of the device and monitoring the status of
various functions. These registers are mapped into 4K of the PCI bus memory address space. These functions
include all 8 channel UART’s interrupt control and status, 16-bit general purpose timer control and status,
multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision.
And lastly, each UART channel has its own set of internal UART configuration registers for its own operation
control and status reporting. All 8 sets of channel registers are embedded inside the device configuration
registers space, which provides faster access. The following paragraphs describe all 3 sets of registers in
detail.
FIGURE 5. THE XR17D158 REGISTER SETS
D evic e C onfig ur ation and
U AR T [7:0] C onfig uration
R eg isters are mapped on
to the Base Address
R eg ister (BAR ) in a 4K-
byte of memor y addr es s
space
PC I Local Bus
Inter fac e
PC I Local Bus
C onfig uration Space
R eg isters for Plug -
and-Play Auto
C onfig uration
Vendor and Sub- vendor ID
and Product M odel N umber
in Exter nal EEPR O M
C hannel 0
IN T , M PIO ,
T IM ER ,R EG
C hannel 0
C hannel 1
C hannel 2
C hannel 3
C hannel 4
C hannel 5
C hannel 6
C hannel 7
0 x0 0 0 0
0 x0 0 8 0
0 x0 2 0 0
0 x0 4 0 0
0 x0 6 0 0
0 x0 8 0 0
0x0A 00
0x0C 00
0 x0 E 0 0
0x0F F F
D evic e C onfig ur ation R eg is ter s
8 channel Interrupts,
M ultipurpose I/O s,
16-bit T imer/C ounter,
Sleep, R eset, D VID , D R EV
U AR T [7:0] C onfig uration
R eg isters
16550 C ompatible and EXAR
Enhanced R eg isters
PCIREG S-1
2.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto
configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the
device vendor and sub-vendor data required by the auto-configuration setup.
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